Professional Summary
High-speed PCB design engineer: DDR4/DDR5, PCIe Gen4/5, 10-25G SerDes, full SI/PI simulation, stack-up definition and DFM-clean release packages.
Engineering Expertise
PCB DesignSignal IntegrityHigh-Speed DigitalDFM
Technical Skills
PCB DesignAltiumSignal IntegrityDDR4PCIePower Integrity
Certifications
- IPC CID+ (Certified Interconnect Designer) — IPC (2018)
- Signal Integrity Specialist — Teledyne LeCroy Academy (2020)
Work Experience
- Principal PCB Design Engineer· Sasken Technologies2019 — Present
Owned 18-layer server and edge-AI boards with PCIe Gen4 and DDR4; all designs passed SI compliance on first spin.
- Hardware Design Engineer· Bosch India2015 — 2019
Automotive ECU boards, CAN-FD and Ethernet AVB, with full DFM/DFT reviews and EMC design rules.
- PCB Layout Engineer· Mistral Solutions2012 — 2015
Layout for SBCs and carrier boards on Altium and Allegro.
Education
- MTech VLSI & Embedded Systems — NIT Karnataka (2012)
- BTech Electronics & Communication — Anna University (2010)
Research & Publications
- Practical stack-up strategies for DDR5 on cost-constrained boards — DesignCon India (2023)
Languages
- English · Fluent
- Malayalam · Native
- Hindi · Professional
Availability
available
Contact / Hire
Engagements with Priya Nair run through VoltLancer. Share your engineering brief and our team arranges the introduction, interview and two-week risk-free trial.
Portfolio projects
No published portfolio projects yet.